Download 60-GHz CMOS Phase-Locked Loops by Hammad M. Cheema, Reza Mahmoudi, Arthur H.M. van Roermund PDF

By Hammad M. Cheema, Reza Mahmoudi, Arthur H.M. van Roermund

The promising excessive info fee instant purposes at millimeter wave frequencies often and 60 GHz specifically have received a lot consciousness lately. in spite of the fact that, demanding situations relating to circuit, structure and measurements in the course of mm-wave CMOS IC layout must be conquer earlier than they could develop into workable for mass market.

60-GHz CMOS Phase-Locked Loops concentrating on phase-locked loops for 60 GHz instant transceivers elaborates those demanding situations and proposes suggestions for them. The procedure point layout to circuit point implementation of the full PLL, besides separate implementations of person elements reminiscent of voltage managed oscillators, injection locked frequency dividers and their mixtures, are incorporated. moreover, to meet a few transceiver topologies concurrently, flexibility is brought within the PLL structure by utilizing new dual-mode ILFDs and switchable VCOs, whereas reusing the low frequency elements on the related time.

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Extra info for 60-GHz CMOS Phase-Locked Loops

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This corresponds to a 500 MHz and 2 GHz frequency jump at 60 GHz, respectively. The settling time obtained is about 1 ms as shown in Fig. 13. The ideal output of a frequency synthesizer is a pure sinusoidal waveform. However, just like any other integrated electronic system, non-idealities such as noise degrade the spectrum purity of the output signal. This can potentially result (among other negative impacts) in lower sensitivity, poor blocking performance on the receiver side, and increased spectral emissions on the transmitter side.

Therefore, in this work, on a layout level this problem is addressed by defining separate power supply domains for analog and digital components which are isolated from each other using the techniques mentioned earlier. Furthermore, this problem is also tackled on a circuit level and will be explained in subsequent chapters. 48 3 Layout and Measurements at mm-Wave Frequencies Probe G S S G G G P G S G G L-shaped ground corner DC-Probe S P Probe G G Ground ring S G Probe Fig. 2 Measurement Setups At low frequencies, as a matter of tradition, an under-par performance of a circuit is usually attributed to inaccuracies of device models, analysis or circuit design flaws.

The solution of this is to move the measurement plane (or reference plane) from inside the equipment to the real device-under-test (DUT). This is accomplished by two processes namely calibration and de-embedding by which the undesired contributions in the measurements are “backed-out” or “subtracted” from the overall measurement. This is illustrated in Fig. 15. The first procedure by which the measurement plane is shifted from the equipment to the probe-tip is called calibration. In this process, prior to measuring the DUT, commercial impedance standard substrates (ISS) are used to account for imperfections of VNA, cables, connectors and probes.

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